The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a field-effect transistor and methods of forming a structure for a field-effect transistor.
Device structures for a field-effect transistor generally include a source, a drain, and a gate electrode configured to switch carrier flow in a channel between the source and drain. The channel of a planar field-effect transistor is arranged in a semiconductor layer below the gate electrode. When a control voltage exceeding a designated threshold voltage is applied to the gate electrode during operation, carriers flow in the channel between the source and drain to produce a device output current.
Nanosheet field-effect transistors represent a type of non-planar field-effect transistor that may promote additional packing density increases in an integrated circuit. A nanosheet field-effect transistor includes multiple nanosheet channel layers that are arranged in a patterned layer stack over a top surface of a substrate and source/drain regions that are connected with the ends of the nanosheet channel layers. The nanosheet channel layers are initially arranged in the patterned layer stack with sacrificial layers containing a material (e.g., silicon-germanium) that alternate with the nanosheet channel layers and that can be etched selectively to the material (e.g., silicon) constituting the nanosheet channel layers. The source/drain regions may be formed by epitaxially growing semiconductor material from the ends of the nanosheet channel layers and from the substrate adjacent to the layer stack. The sacrificial layers are etched and removed in order to release the nanosheet channel layers and to provide spaces for the formation of a gate stack. Sections of the gate stack may surround all sides of the individual nanosheet channel layers in a gate-all-around arrangement. During operation, the horizontal flow of carriers in the nanosheet channel layers produces the device output current.
To optimize performance, dielectric isolation is needed to electrically isolate the source/drain regions from the substrate in order to suppress leakage current through the substrate beneath the patterned layer stack and the gate stack and between the source/drain regions. An approach is to rely on the buried insulator layer of a silicon-on-insulator substrate to provide the needed dielectric isolation. For a bulk substrate, an approach is to form a punch-through stopper region beneath the patterned layer stack and the gate stack that is effective to suppress the leakage current. However, shallow trench isolation is required during the fabrication process flow to provide support for the nanosheet channel layers when removing the sacrificial layers prior to forming the gate stack.
Improved structures for a field-effect transistor and methods of forming a structure for a field-effect transistor are needed.